Server/CMS/ComposableMemoryAppliance

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Welcome to the OCP Server - CMS - Composable Memory Appliance (CMA) Hardware Sub-project

OCP Composable Memory Appliance (CMA) Hardware is a sub-project within the Server - CMS Sub-Project.

Leadership

Scope

This team shall leverage the existing initial CMA CLA contribution, use it as a launching pad to any exploratory studies that allow us to learn and explore and standardize the next generation OCP standardized architectural enhancements needed to reduce cost, improve latency and bandwidth performance and increase the number of clustered nodes that can connect into this pooled memory appliance.

The current CLA based CMA contribution is limited to:

  • 1. CMA Hardware charter, which will impact the Server level hardware
  • 2. The appliance mechanical packaging and architectural specification, including blade form factor details, blade upstream and power connector types and pinouts;
  • 3. The PSU card pinout and mechanical form factor;
  • 4. The RunBMC firmware and specification;
  • 5. The fans module design, connector and pinout;
  • 6. The enclosure Midplane PCBA mechanical form factor and high-level architectural design details, and;
  • 7. All midplane connector types and pinouts.

The following subject matters re specifically out of scope of the initially contributed CMA CLA, but will be included in future CMA collaborative efforts:

  • 1. FPGA RTL
  • 2. Future Silicon
  • 3. All Board Schematics
  • 4. All Board Layout/Gerber Files

Charter

Provide a TCO-optimized solution to the Memory-wall and Stranded-resource challenge. We are currently aiming towards a CXL pooled memory with Non-blocking bandwidth performance and to offer a <= 400ns full command-to-data round trip latency in order to positively impact and enable ~80% or more of the cloud based applications. Our goal is to create openness, efficiency, and optimized TCO for scaling pooled memory capacity and bandwidth while maintaining ~2x NUMA latency, which can improve sustainability through DDR4 recycling and reduced overall power per GB of memory capacity scaling.

Documents

  • Coming Soon

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